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ICS664-03
Digital Video Clock Source
Description
The ICS664-03 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS664-03 uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. The ICS664-03 is suitable for Digital Video STB and DTV applications. For Transmitter application use ICS664-01 or ICS664-02. For audio sampling clocks generated from 27 MHz, use the ICS661. Please contact ICS if you have a requirement for an input and output frequency not included in this document. ICS can rapidly modify this product to meet special requirements.
Features
* * * * * * * * *
Packaged in 16-pin TSSOP Available in Pb (lead) free package Clock or crystal input provides flexibility Low phase noise supports enhanced SNR Lowest jitter in class at 100 ps Exact (0 ppm) multiplication ratios Power-down mode lowers power consumption Improved phase noise over ICS660 Provides High definition Video clocks for 720p, 1080i and 1080p YUV standards
Block Diagram
VDD (P2) VDD (P3) VDDO VDD (P14)
X2 Crystal Oscillator
X1/REFIN
SELIN S3:0
4
PLL Clock Synthesis
CLK
GND (P6)
GND (P5)
GND (P13)
MDS 664-03 B Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 091404 tel (408) 297-1201
www.icst.com
ICS664-03 Digital Video Clock Source
Pin Assignment
X1/REFIN VDD VDD S0 GND GND S3 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 N/C VDD GND SELIN VDDO S1 CLK
Output Clock Selection Table
S3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input Frequency (MHz)
27 27 27 13.5 13.5 27 27 74.25 74.175824 74.25 74.175824 54 54 54 27
Output Frequency (MHz)
Power down 27 (passthrough) 74.25 74.175824 74.25 74.175824 148.5000 148.351648 54
54
27 27 74.25 74.175824 13.5 13.5
16-pin TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X1/REFIN VDD VDD S0 GND GND S3 S2 CLK S1 VDDO SEL GND VDD NC X2
Pin Type
Input Power Power Input Power Power Input Input Output Input Power Input Power Power -- Input Power supply for crystal oscillator. Power supply for PLL.
Pin Description
Connect this pin to a crystal or clock input
Output frequency selection. Determines output frequency per table above. Internal pull-up. Ground for PLL. Ground for PLL for Crystal Osillator. Output frequency selection. Determines output frequency per table above. Internal pull-up. Output frequency selection. Determines output frequency per table above. Internal pull-up. Clock output. Output frequency selection. Determines output frequency per table above. Internal pull-up. Power supply for output stage. Low for clock input, high for crystal. Internal pull-up. Ground for Output. Power supply. No connect. Do not connect to anything. Connect this pin to a crystal. Leave open if using a clock input.
MDS 664-03 B
2
Revision 091404 tel (408) 297-1201
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-03 Digital Video Clock Source
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Load Capacitors
If a crystal is used, the device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS664-03 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS664-03 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI and obtain the best signal integrity, the 33 series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS664-03. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Recommended Power Supply Connection for Optimal Device Performance
V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead V D D P in
B ulk D ecoupling C apacitor (such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
All power supply pins must be connected to the same voltage, except VDDO, which may be connected to a lower voltage in order to change the output level. To achieve the absolute minimum jitter, power the part with a dedicated LDO regulator, which will provide high isolation from power supply noise. Many companies produce very small, inexpensive regulators; an example is the National Semiconductor LP2985.
MDS 664-03 B
3
Revision 091404 tel (408) 297-1201
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-03 Digital Video Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS664-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 5.5 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.0
Typ.
Max.
+70 +3.6
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70 C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Nominal Output Impedance Input Capacitance Internal Pull-up Resistor
Symbol
VDD VDDO IDD VIH VIL VOH VOH VOL IOS ZOUT CIN RPU
Conditions
Min.
3.0 2.5
Typ.
Max.
3.6 VDD
Units
V V mA V
No Load 2
35 0.8
V V V
IOH = -4 mA IOH = -20 mA IOL = 20 mA Each output Input pins
VDD-0.4 2.4 0.4 65 20 7 120
V mA pF k
MDS 664-03 B
4
Revision 091404 tel (408) 297-1201
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-03 Digital Video Clock Source
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70 C
Parameter
Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Duty Cycle Power-up Time Power-down Time Jitter, short term Jitter, long term Single Sideband Phase Noise Actual Mean Frequency Error versus Target
Symbol
tOR tOF tOD tPU tPD
Conditions
20% to 80%, 15 pF load 80% to 20%, 15 pF load at VDD/2, 15 pF load Valid power on to valid output Power off to clock disable 10 s delay 10 kHz offset
Min.
Typ.
Max.
28 1.5 1.5
Units
MHz ns ns % ms s ps p-p ps p-p dBc ppm
40
49 to 51 1 10 100 200 -120 0
60
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 664-03 B
5
Revision 091404 tel (408) 297-1201
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-03 Digital Video Clock Source
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters Symbol Min Max Inches Min Max
16
E1 IN D EX AR EA
E
1
2
D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A 2 A 1
A
c
-Ce
b S E A T IN G P LA N E L
aaa C
Ordering Information
Part / Order Number
ICS664G-03 ICS664G-03T ICS664G-03LF ICS664G-03LFT
Marking
664G-03 664G-03 664G03LF 664G03LF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
"LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 664-03 B
6
Revision 091404 tel (408) 297-1201
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126
www.icst.com

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